M.S. student at the School of Integrated Circuits, Shanghai Jiao Tong University, specializing in chip front-end design and verification. Currently interning at ByteDance's AI Chip division, working on functional-level modeling and simulation toolchain development for AI accelerators. Deeply interested in computer architecture, AI accelerator design, and RISC-V processor development.
Advisor: Prof. XXX, Shanghai Jiao Tong University
韩汪洋
Undergraduate Thesis · SJTU, 2026
Designed a complete SoC system based on the RISC-V C908 processor with AXI/AHB/APB three-level bus architecture, implementing memory and peripheral integration. Completed AXI-to-UCIe interface adaptation logic for address mapping and data path conversion, with C-level system verification.
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Innovation Project · SJTU, 2025
Implemented CNN hardware accelerator covering architecture design, RTL design, verification platform, and logic simulation. Synthesized on SMIC 0.18μm process achieving 200K/s input feature map processing at 96.7MHz clock frequency, 1.1W power consumption, and 54.18mm² area.
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National IC Innovation Competition · First Prize, 2025
Developed AI edge application on EIC7700X platform covering model training, quantization, compilation, and deployment. Implemented face detection, emotion recognition, and multimodal interaction using Yolo, ResNet34, and Qwen2 for real-time student engagement monitoring.